Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 80)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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CAN 1 INTERRUPT REGISTER (C1IR)
7 6 5 4 3 2 1 0
SFR E5h
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
C1IR.7-0
Bit 7-5 CAN 1 Interrupt Indicator 7-0 This register indicates the status of the interrupt
source associated with the CAN 1 module. Reading this register after the
generation of a CAN 1 Interrupt will identify the interrupt source as shown in the
table below. This register is cleared to 00h following a reset.
C1IR.7-0 Priority Interrupt Source
00h N/A No Pending Interrupt
01h 1 (highest) Change in the CAN 1 Status Register
02h 2 Message 15
03h 3 Message 1
04h 4 Message 2
05h 5 Message 3
06h 6 Message 4
07h 7 Message 5
08h 8 Message 6
09h 9 Message 7
0Ah 10 Message 8
0Bh 11 Message 9
0Ch 12 Message 10
0Dh 13 Message 11
0Eh 14 Message 12
0Fh 15 Message 13
10h 16 (lowest) Message 14
The C1IR value will not change unless the previous interrupt source has been
acknowledged and removed (i.e., software read of the C1S register or clearing of
the appropriate INTRQ bit), even if the new interrupt has a higher priority. If two
enabled interrupt sources become active simultaneously, the interrupt of higher
priority will be reflected in the C1IR value.
The CAN 1 interrupt source into the interrupt logic is active whenever C1IR is not
equal to 00h. Changes in the C1IR value from 00h to a non-zero state, indicate the
first interrupt source detected by the CAN module following the non-active
interrupt state. The C1IR interrupt values displayed in C1IR will remain in place
until the respective interrupt source is removed, independent of other higher (or
lower) priority interrupts that become active prior to clearing the currently
displayed interrupt source.
When the current CAN interrupt source is cleared, C1IR will change to reflect the
next active interrupt with the highest priority. The Status Change interrupt will be
asserted if there has been a change in the CAN 1 Status Register (if enabled by the
appropriate ERIE and/or STIE bit) and the CAN Status Interrupt state is set. A
message center interrupt will be indicated if the INTRQ bit in the respective CAN
Message Control Register is set.