Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 99)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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Having selected the memory configuration, the following SFR settings affect the example memory map:
SA EQU 1 ; Use 1KB stack in on-chip XDATA space
IDM EQU 2 ; 2 = 4KB on-chip SRAM location X:0x400000 – X:400FFF
CMA EQU 1 ; 1 = CAN0 X:0x401000 – X:0x4010FF
; CAN1 X:0x401100 – X:0x4011FF
P4CNT5_3 EQU 110B ; 110B = 512kB (A18-A0 enabled)
P4CNT2_0 EQU 101B ; 101B = enable CE0, CE1
P5CNT2_0 EQU 110B ; 110B = enable PCE0, PCE1, PCE2
When complete, chip-enable signals should be active when indicated below:
CHIP-ENABLE ACCESS ACTIVITY
CE0 accesses with PSEN\ Program fetches from low 512kB and MOVC read to 07FFFFH
CE1 access with PSEN\ MOVC read to 080000H
PCE0 access with RD\ MOVX access to 07FFFFH
PCE1 access with RD\ MOVX access to 080000H
PCE1 access with RD\ MOVX access to 0FFFFFH
PCE2 access with RD\ MOVX access to 100000H
—
MOVX operation to 400000H accesses internal XRAM and can
be verified by viewing the contents of ACC inside of the simulator