Can 0 i, Nterrupt, Egister – Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement User Manual

Page 42: C0ir)

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High-Speed Microcontroller User’s Guide: DS80C390 Supplement

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arbitration field (identifier and remote retransmission request).

Bit 0 Error

: Indicates that the CAN attempted to transmit a message and that

when a dominant bit was transmitted, the CAN bus was found to have a
recessive bit level. This error is not generated when the bit is a part of the
arbitration field. The Bit 0 Error is set each time a recessive bit is received
during the Busoff recovery period.

CRC Error

: Generated whenever the calculated CRC of a received message does

not match the CRC embedded in the message.

CAN 0 INTERRUPT REGISTER (C0IR)

7 6 5 4 3 2 1 0

SFR A5h

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset

C0IR.7-0
Bit 7-5

CAN 0 Interrupt Indicator 7-0 This register indicates the status of the
interrupt source associated with the CAN 0 module. Reading this register
after the generation of a CAN 0 Interrupt will identify the interrupt source as
shown in the table below. This register is cleared to 00h following a reset.

C0IR.7-0 Priority

Interrupt

Source

00h

N/A

No Pending Interrupt

01h

1 (highest)

Change in the CAN 0 Status Register

02h 2

Message

15

03h 3

Message

1

04h 4

Message

2

05h 5

Message

3

06h 6

Message

4

07h 7

Message

5

08h 8

Message

6

09h 9

Message

7

0Ah 10

Message

8

0Bh 11

Message

9

0Ch 12

Message

10

0Dh 13

Message

11

0Eh 14

Message

12

0Fh 15

Message

13

10h

16 (lowest)

Message 14

The C0IR value will not change unless the previous interrupt source has been
acknowledged and removed (i.e., software read of the C0S register or clearing of
the appropriate INTRQ bit), even if the new interrupt has a higher priority. If two
enabled interrupt sources become active simultaneously, the interrupt of higher
priority will be reflected in the C0IR value.
The CAN 0 interrupt source into the interrupt logic is active whenever C0IR is not
equal to 00h. Changes in the C0IR value from 00h to a non-zero state, indicate the

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