Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 60)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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PDCE2
Bit 2 Program/Data Chip Enable 2. This bit selects whether the CE2 signal
functions as the chip enable for external program memory only (PDCE=0), or as
a merged chip enable for program and data memory (PDCE=1). When PDCE=1,
the microprocessor will use the PSEN signal instead of the RD signal when
reading from external MOVX memory. The Port 4 Control register (P4CNT)
determines the memory range associated with CE2 . This bit is ignored if CE2
has not been previously enabled by the Port 4 Control register.
PDCE1
Bit 1 Program/Data Chip Enable 1. This bit selects whether the CE1 signal functions
as the chip enable for external program memory only (PDCE=0), or as a merged
chip enable for program and data memory (PDCE=1). When PDCE=1, the
microprocessor will use the PSEN signal instead of the RD signal when reading
from external MOVX memory. The Port 4 Control register (P4CNT) determines
the memory range associated with CE1. This bit is ignored if CE1 has not been
previously enabled by the Port 4 Control register.
PDCE0
Bit 0 Program/Data Chip Enable 0. This bit selects whether the CE0 signal
functions as the chip enable for external program memory only (PDCE=0), or as
a merged chip enable for program and data memory (PDCE=1). When PDCE=1,
the microprocessor will use the PSEN signal instead of the RD signal when
reading from external MOVX memory. The Port 4 Control register (P4CNT)
determines the memory range associated with CE0 . This bit is ignored if CE0
has not been previously enabled by the Port 4 Control register.
TIMED ACCESS REGISTER (TA)
7 6 5 4 3 2 1 0
SFR C7h TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
W = Unrestricted Write, -n = Value after Reset
TA.7-0
Bits 7-0 Timed Access. Correctly accessing this register permits modification of timed-
access protected bits. Write AAh to this register first, followed within 3 cycles by
writing 55h. Timed-access protected bits can then be modified for a period of 3
cycles measured from the writing of the 55h.