Slave address mask enable register 0 (saden0), Slave address mask enable register 1 (saden1), Lave – Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement User Manual
Page 53: Ddress, Nable, Egister, 0 (saden0), 1 (saden1)
High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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PT0
Bit 1
Timer 0 Interrupt. This bit controls the priority of Timer 0 interrupt.
0 = Timer 0 is determined by the natural priority order.
1 = Timer 0 is a high priority interrupt.
PX0
Bit 0
External Interrupt 0. This bit controls the priority of external interrupt 0.
0 = External interrupt 0 is determined by the natural priority order.
1 = External interrupt 0 is a high priority interrupt.
SLAVE ADDRESS MASK ENABLE REGISTER 0 (SADEN0)
7 6 5 4 3 2 1 0
SFR B9h
SADEN0.7 SADEN0.6 SADEN0.5 SADEN0.4 SADEN0.3 SADEN0.2 SADEN0.1 SADEN0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
SADEN0.7-0
Bits 7-0
Slave Address Mask Enable Register 0. This register functions as a mask when
comparing serial port 0 addresses for automatic address recognition. When a bit
in this register is set, the corresponding bit location in the SADDR0 register will
be exactly compared with the incoming serial port 0 data to determine if a
receiver interrupt should be generated. When a bit in this register is cleared, the
corresponding bit in the SADDR0 register becomes a “don’t care” and is not
compared against the incoming data. All incoming data will generate a receiver
interrupt when this register is cleared.
SLAVE ADDRESS MASK ENABLE REGISTER 1 (SADEN1)
7 6 5 4 3 2 1 0
SFR BAh
SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3 SADEN1.2 SADEN1.1 SADEN1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
SADEN1.7-0
Bits 7-0
Slave Address Mask Enable Register 1. This register functions as a mask when
comparing serial port 1 addresses for automatic address recognition. When a bit
in this register is set, the corresponding bit location in the SADDR1 register will
be exactly compared with the incoming serial port 1 data to determine if a
receiver interrupt should be generated. When a bit in this register is cleared, the
corresponding bit in the SADDR1 register becomes a “don’t care” and is not
compared against the incoming data. All incoming data will generate a receiver
interrupt when this register is cleared.