ADLINK PCI-9810 - Manual (Page 26)

14 Hardware Information
External Clock 0
The external clock 0 (J5) is a sine wave signal that is converted to
a TTL signal inside the PCI-9812/9810. This signal is AC coupled.
The input impedance of external clock 0 is 50
Ω and the input level
is 2 V peak-to-peak.
Note that the external clock frequency is the system clock. The
maximum A/D clock frequency is half of the system clock. When
using the external sine clock for PCI-9812, take note that the
frequency of the sine clock must be above 300 KHz. Otherwise the
sine clock will be converted into a digital clock with a long rise
time. When the rise time of a clock signal is too long, the CPLD
may not work as specified and the real sample clock fed into the
ADC will not be continuous. This explains why users will see a
different sampled waveform when using a slower sine wave clock.
If slower sampling rate is necessary when using PCI-9812/9810,
you could feed a sine wave clock that has the frequency higher
than 300 KHz, and use the clock divisor to obtain a slower
sampling rate.
External Clock 1
The external clock 1 (JP1 pin 1) is a digital clock. The input
impedance is 50
Ω and the input level into the 50 ohm-load should
be between 2.4 V and 5 V. This signal is DC coupled.
Digital Input
The PCI-9812/9810 has four digital inputs: an external digital
trigger (JP1 pin3) and three general-purpose digital inputs (JP1
pin 5, 7, and 9). These inputs are TTL-compatible with 10 K
Ω pull-
down resistors.
The PCI-9812/9810 also performs an automatic configuration of
the IRQ and I/O port address. There is no need to set any
configuration, as you would use in an ISA form factor DAQ card.
For system reliability, it is necessary to manually assign some
critical settings for analog input/output as these settings will not be
changed after your data acquisition system configuration is
decided. The software package cannot change this configuration
when the system is running.