Adc clock divisor register – ADLINK PCI-9810 User Manual
Page 31
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Registers
19
ADC Clock Divisor Register
Feeding the ADC source clock to a clock frequency divider gener-
ates the ADC sampling clock. The output of the frequency divider
becomes the sampling clock. The frequency of the ADC sampling
clock is:
Frequency of source clock / ADC clock divisor
Address: BASE+04h
Attribute: Write only
Data Format:
NOTE
The minimum value of this register is 2, and the DIV0 is
hardwired to 0.
Bit
7
6
5
4
3
2
1
0
Base+4
DIV7
DIV6
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
Base+5
DIV15 DIV14 DIV13 DIV12
DIV11
DIV10
DIV9
DIV8
Base+6
—
—
—
—
—
—
—
—
Base+7
—
—
—
—
—
—
—
—
DIV15...0
AD clock frequency devisor.
—
Any value
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