ADLINK PCI-9810 - Manual (Page 48)

36 Operation Theory
5.4 Clock Source Control
The AD clock source determines how the board regulates the
timing of conversions when acquiring multiple samples from a
single-channel or from a group of multiple channels. The A/D clock
sources on the PCI-9812/9810 must use a pacer clock, but not
single-shot as the A/D converters are in a pipelined structure, that
require eight conversion clocks to complete the conversion of
digital data.
A/D Clock Sources
The A/D converters operate under the paced mode, which uses
pacer clock for A/D conversion at a fixed rate. PCI-9812/9810
supports three clock sources for analog input conversion
X Internal Pacer Clock (default)
An onboard timer/counter is used as the internal A/D pacer
clock. The frequency of the pacer is software-controllable. The
maximum pacer signal rate is 40 MHz / 2 = 20 MHz, which is
also the maximum sampling rate of PCI-9812/9810. Note that
40 MHz is the onboard clock. Feeding the clock source into a
frequency divider generates the ADC sampling frequency. The
following formula determines the ADC sampling frequency:
Sampling Rate = Frequency of Source Clock / ADC
Clock Divisor
NOTE The ADC Clock Divisor must be 2, 4, 6, 8,…65534 (max).
X External Pacer Clock
You can connect an external pacer clock to the EXTCLK1 (pin
1) on JP1 (for square wave) or Ext. Sine wave clock (for sine
wave). Since you can handle the external signal with outside
devices, the conversion rate of this mode is more flexible than
the previous mode. When the external clock is selected, the
frequency divider as mentioned also divides this external clock.
Therefore the frequency of the external clock should be at least
twice the sampling frequency. The formula is shown below:
Sampling Rate = Frequency of Source Clock / ADC
Clock Divisor