ADLINK PCI-9810 - Manual (Page 52)

40 Operation Theory
Bus-mastering Data Transfer
PCI bus-mastering DMA is necessary for high speed DAQ in order
to utilize the maximum PCI bandwidth. The bus-mastering
controller—built into the AMCC-5933 PCI controller ASIC—
controls the PCI bus when it becomes the master of the bus. Bus-
mastering reduces the size of onboard memory and CPU loading
since data is directly transferred to the computer’s memory without
CPU intervention.
The bus-mastering DMA provides the fastest data transfer rate on
the PCI bus. Once the analog input operation starts, control
returns to your program. The hardware temporarily stores the
acquired data into the onboard A/D FIFO and transfers the data to
a user-defined DMA buffer memory in the computer.
NOTE Even when the acquired data length is less than the
FIFO, the AD data is directly transferred to the host mem-
ory by bus-mastering DMA.
As DMA transfer mode is very complex to program, ADLINK
recommends using a high-level program library to control the card.
If you want to apply a software that can handle the DMA bus
master data transfer, visit www.amcc.com for more information on
the PCI controller.
Host Memory Operation
The DMA data transfer does not allow processing of AD data
simultaneously with the data transfer. You must process the AD
data after the completion of one DMA cycle. If the total data
throughput in your application is relatively high (>20 MB/s), the
processing time of AD data and the CPU computation power
consumption must be considered. For example, if the CPU can
only process data at a rate of 10 MB/s and you want to
continuously acquire data at the rate of 20 MB/s; the FIFO
eventually becomes full and data acquisition becomes
discontinuous.