ADLINK PCI-9810 - Manual (Page 44)

32 Operation Theory
5.3 Trigger Source Control
When performing trigger acquisition in the PCI-9812/9810, the
following parameters have to be specified before DMA operation
starts:
X Clock source. Refer to section 5.4
X Clock rate. Refer to section 5.4
X Trigger sources. Refer to next section.
X Trigger level. The trigger event occurs when the trigger sig-
nal crosses the specified trigger voltage. Refer to Trigger
Level Register section for the relationship between the 8-bit
trigger level and the trigger voltage.
The trigger is detected while the trigger event occurs. For
post-trigger and middle-trigger, the data acquisition is per-
formed after the trigger event. However, the time that the
AD conversion starts is 350 ns slower than the trigger
detection time. This 350 ns delay has some minor effect to
high-speed data acquisition.
X Trigger polarity. Trigger slope with a 0 value indicates a
positive trigger while a 1 value indicates a negative trigger.
Trigger Sources
X Internal trigger
This is a software trigger. The trigger event occurs when you
call _9812_AD_DMA_Start( ) function to start the operation.
X External analog trigger
You can use the signal on any analog input channel (CH0,
CH1, CH2, or CH3) as the trigger signal for external analog
trigger. Below are two conditions for analog triggers.
Z Positive-slope trigger
The trigger event occurs the first time the trigger signal (analog
input signal) changes from a voltage that is lower than the