ADLINK aTCA-9710 - Manual (Page 11)

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2.3 Board Layout
2.3.1 aTCA-9710 Board Layout - Component Side
Location Description Location Description
CN1 XL710 JTAG debug header SW1 Reserved for PCH debug
CN2 XL710 JTAG debug header SW2 Clear CMOS
CN7 Ground connection SW3 IPMC Programming mode
DIMM_AB/CD DDR4 DIMM A-D SW4 IPMC Mode Select
DIMM_EF/GH DDR4 DIMM E-H SW6 HW Reset Button
J3/4 Zone 3 to RTM SW7 Reserved for XL710 debug
PSU1 400W -48V DC/DC module SW8 Reserved for XL710 debug
PSU2 400W Hot Swap Power Module
CPU1
CPU2
J3
SW4
SW1
CN7
DIMM_GH
CN2
J4
SW8
PSU1
CN1
DIMM_CD
SW7
DIMM_EF
DIMM_AB
PSU2
B1 A1
SW3
C1 D1
B2 A2 C2 D2
H1 G1 E1 F1
H2 G2 E2 F2