ADLINK CoreModule 920 - Manual (Page 34)

Chapter 3 Hardware
28 Reference Manual CoreModule 920
Ethernet Interfaces
The CoreModule 920 supports two Gigabit Ethernet interfaces. The first Ethernet interface originates from
the 82579LM PHY transceiver, which occupies one PCI Express lane and supports the internal MAC
(Media Access Controller) in the PCH. The second Ethernet interface is implemented through the 82574IT
Ethernet controller, which occupies one PCI Express lane and generates its own Gigabit Ethernet signals.
The Ethernet function supports multi-speed operation at 10/100/1000 Mbps and operates in full-duplex at all
supported speeds or half duplex at 10/100 Mbps while adhering to the IEEE 802.3x flow control
specification. The Ethernet interface offers the following features:
• Full duplex support at 10 Mbps, 100 Mbps, or 1000 Mbps
• Half duplex support at 10 Mbps and 100 Mbps
• In full duplex mode, the Ethernet controller adheres to the IEEE 802.3x Flow Control specification
• In half duplex mode, performance is enhanced by a proprietary collision reduction mechanism
• IEEE 802.3 compatible physical layer to wire transformer
• IEEE 802.3u Auto-Negotiation support
• Fast back-to-back transmission support with minimum interframe spacing (IFS)
• IEEE 802.3x auto-negotiation support for speed and duplex operation
• On-board magnetics (Ethernet isolation transformers)
Table 3-8 describes the pin signals of the Ethernet GLAN1 interface, which consists of a two-row, 10-pin
vertical header with odd/even (1,2) pin sequence, and 0.100" (2.54mm) pitch.
Note: The shaded table cells denote ground.
Table 3-8. GLAN1 Interface Pin Signal Descriptions (H11)
Pin # Signal Description
1 MDI1+ Media Dependent Interface 1 +/-
2 MDI1-
3 MDI2+ Media Dependent Interface 2 +/-
4 MDI2-
5 MDI0+ Media Dependent Interface 0 +/-
6 MDI0-
7 MDI3+ Media Dependent Interface 3 +/-
8 MDI3-
9 GND Ground
10 GND
NOTE The magnetics (isolation transformer, T1) for the Ethernet connector is included
on the CoreModule 920.