ADLINK CoreModule 920 - Manual (Page 38)

Chapter 3 Hardware
32 Reference Manual CoreModule 920
User GPIO Interface
The CoreModule 920 provides GPIO pins for customer use, routing the signals from the PCH chipset to the
J26 and J27 headers. An example test application and source code reside in each BSP directory of the
CoreModule 920 Support Software QuickDrive.
For instructions on using the example applications, refer to the GPIO Readme in each BSP directory of the
QuickDrive. For more information about the GPIO pin operation, refer to the PCH BD82QM67 datasheet at:
http://www.intel.com/Assets/PDF/datasheet/324645.pdf
Table 3-13 describes the pin signals of the GPIO1 interface, which provides a 6-pin, single-row header with
0.079" (2mm) pitch.
Note: The shaded areas denote ground. All GPIO pins are in the Core Power Well of the PCH.
Table 3-14 describes the pin signals of the GPIO2 interface, which provides a 6-pin, single-row header with
0.079" (2mm) pitch.
Note: The shaded table cells denote ground. All GPIO pins are in the Core Power Well of the PCH.
Table 3-13. User GPIO1 Interface Pin Signal Descriptions (J26)
Pin # Signal Description
1 PCH_GPIO71 User defined
2 PCH_GPIO70 User defined
3 PCH_GPIO69 User defined
4 PCH_GPIO68 User defined
5 GND Ground
6 GND Ground
Table 3-14. User GPIO2 Interface Pin Signal Descriptions (J27)
Pin # Signal Description
1 PCH_GPIO35 User defined
2 PCH_GPIO36 User defined
3 PCH_GPIO37 User defined
4 PCH_GPIO38 User defined
5 GND Ground
6 GND Ground