ADLINK CoreModule 720 - Manual (Page 34)

Chapter 3 Hardware
28 Reference Manual CoreModule 720
Note: The shaded table cells denote power or ground.
Table 3-11 lists the pin signals of the LVDS video header, which provides 20 pins, 2 rows, odd/even pin
sequence (1, 2) with 0.079" (2mm) pitch.
Note: The shaded table cells denote power or ground.
20 SDVO_I2C_CLK I2C control signal (Clock) for SDVO device
21 SDVO_I2C_DAT I2C control signal (Data) for SDVO device
22 RESET Reset signal
23 +3.3V_1 +3.3 Volt Power 1
24 +2.5V +2.5 Volt Power
25 +5V_1 +5 Volt Power 1
26 GND8 Ground 8
27 SDVO_TVCLKIN- SDVO TV-Out Synchronization Clock Input - Negative
28 SDVO_TVCLKIN+ SDVO TV-Out Synchronization Clock Input - Positive
29 +3.3V_2 +3.3 Volt Power 2
30 +5V_2 +5 Volt Power 2
Table 3-11. LVDS Video Interface Pin Signals (J23)
Pin # Signal Description
1 +12V +12 volts for flat panel and backlight
2 VCC_LVDS_CONN JP3 determines LVDS voltage (+3.3V or +5V)
3 GND Ground
4 GND Ground
5 LVDSA_CLK_P LVDS A Clock Positive
6 LVDSA_CLK_N LVDS A Clock Negative
7 LVDSA_DAT3_P LVDS A DATA Positive Line 3
8 LVDSA_DAT3_N LVDS A DATA Negative Line 3
9 LVDSA_DAT2_P LVDS A DATA Positive Line 2
10 LVDSA_DAT2_N LVDS A DATA Negative Line 2
11 LVDSA_DAT1_P LVDS A DATA Positive Line 1
12 LVDSA_DAT1_N LVDS A DATA Negative Line 1
13 LVDSA_DAT0_P LVDS A DATA Positive Line 0
14 LVDSA_DAT0_N LVDS A DATA Negative Line 0
15 LBKLT_CTL Panel Backlight Control
16 LVDD_EN Enable Panel Power
17 LDDC_CLK Display Data Channel Clock
18 LDDC_DATA Display Data Channel Data
19 LBKLT_EN Enable Backlight Inverter
20 NC Not Connected
Table 3-10. SDVO Interface Pin Signals (J15) (Continued)
Pin # Signal Description