ADLINK CoreModule 720 - Manual (Page 50)

Chapter 4 BIOS Setup
44 Reference Manual CoreModule 720
• North Bridge Chipset Configuration
 Memory Information
• MRC Version XX.XX
• Total Memory XXXX MB (DDR2)
• vBIOS Version XXXX
• IEGD Driver Version N/A
 IGD Mode Select [Disabled;
Enabled, 1MB;
Enabled, 4MB;
Enabled, 8MB;
Enabled, 16MB;
Enabled, 32MB;
Enabled, 48MB;
Enabled, 64MB]
 MSAC Mode Select [Enabled, 512MB;
Enabled, 256MB;
Enabled, 128MB]
 Boot Display Configuration
• Boot Display Device [Integrated LVDS; External DVI/HDMI]
• Flat Panel Type [640x480 18bit;
800x600 18bit;
1024x600 18bit;
1024x768 18bit;
1280x768 18bit;
640x480 24bit;
800x600 24bit;
1024x600 24bit;
1024x768 24bit;
1280x768 24bit]
• South Bridge Chipset Configuration
 SMBUS Controller [Enabled; Disabled]
 Serial IRQ Mode [Continuous; Quiet]
 High Precision Event Timer Configuration
• High Precision Timer [Disabled; Enabled]
 PPM Config
• C-state POPUP [Disabled; Enabled]