ADLINK CoreModule 720 - Manual (Page 35)

Chapter 3 Hardware
CoreModule 720 Reference Manual 29
Power Interface
The CoreModule 720 requires one +5 volt DC power source and provides a shrouded 10-pin, right-angle
header with 2 rows, odd/even pin sequence (1, 2), and 0.100" (2.54mm) pitch. If the +5VDC power drops
below ~4.65V, a low voltage reset is triggered, resetting the system.
The power input header (J19) supplies the following voltage and ground directly to the module:
• 5.0VDC +/- 5%
Note: The shaded table cells denote power or ground.
User GPIO Interface
The CoreModule 720 provides GPIO pins for customer use, routing the signals from the PCH EG20T
chipset to the J3 header. An example test application and source code reside in each BSP directory of the
CoreModule 720 Support Software QuickDrive.
For instructions on using the example applications, refer to the GPIO Readme in each BSP directory of the
QuickDrive. For more information about the GPIO pin operation, refer to the PCH EG20T datasheet at:
http://download.intel.com/embedded/chipsets/datasheet/324211.pdf
Table 3-13 describes the pin signals of the GPIO interface, which consists of a 10-pin header with 2 rows,
odd/even pin sequence (1, 2), and 0.079" (2mm) pitch.
Note: The shaded table cells denote ground.
Table 3-12. Power Interface Pin Signals (J19)
Pin Signal Descriptions
1 GND Ground
2 +5V +5 Volts
3 GND Ground
4 +12V +12 Volts routed to PC/104, PC/104-Plus, and LVDS interfaces
5 GND Ground
6 +3.3V_PCI +3.3 Volts routed to PCI
7 GND Ground
8 +5V +5 Volts
9 GND Ground
10 +5V +5 Volts
Table 3-13. User GPIO Interface Pin Signals (J3)
Pin # Signal from PCH Description
1 GPIO0 User defined
2 GPIO4 User defined
3 GPIO1 User defined
4 GPIO5 User defined
5 GPIO2 User defined
6 GPIO6 User defined
7 GPIO3 User defined
8 GPIO7 User defined
9 GND Ground
10 GND Ground