ADLINK CoreModule 435 - Manual (Page 41)

Chapter 3 Hardware
CoreModule 435 Reference Manual 35
Watchdog Timer
The Watchdog Timer (WDT) restarts the system if an error or mishap occurs, allowing the system to recover
from the mishap, even though the error condition may still exist. Possible problems include failure to boot
properly, loss of control by the application software, failure of an interface device, unexpected conditions on
the bus, or other hardware or software malfunctions.
The WDT can be used both during the boot process and during normal system operation.
• During the Boot process – If the OS fails to boot in the time interval set in the BIOS, the system will
reset.
Enable the WatchDog Function (0 or 1) setting in the Chipset screen of the BIOS Setup. Set the WDT
for a time-out interval in seconds, between 1 and 256, in one second increments. Ensure you allow
enough time for the operating system (OS) to boot. The OS or application must tickle (reset) the WDT
before the timer expires. This can be done by accessing the hardware directly or through a BIOS call.
• During System Operation – An application can set up the WDT hardware through a BIOS call, or by
accessing the hardware directly. Some ADLINK Board Support Packages provide an API to the WDT.
The application must tickle (reset) the WDT before the timer expires or the system will be reset.
• Watchdog Code examples – ADLINK has provided source code examples on the CoreModule 435
Support Software QuickDrive illustrating how to control the WDT. The code examples can be easily
copied to your development environment to compile and test the examples, or make any desired
changes before compiling. Refer to the WDT Readme file in the Sample Code directory on the
CoreModule 435 Support Software QuickDrive.
Power Interface
The CoreModule 435 requires one +5 volt DC power source. If the +5VDC power drops below ~4.65V, a
low voltage reset is triggered, resetting the system.
The power input header (J7) supplies the following voltages and ground directly to the module:
• 5.0VDC +/- 5% @ 1.35 Amps
Table 3-17 describes the pin signals of the Power interface, which uses a 10-pin, right-angle header with 2
rows, odd/even sequence (1, 2), and 0.100" (2.54mm) pitch.
Note: The shaded table cells denote power or ground.
Table 3-17. Power Interface Pin Signal (J7)
Pin Signal Descriptions
1 GND Ground
2 +5V +5 Volts
3 Key/GND Key Pin on connector/Grounded on board
4 +12V +12 volts routed to PC/104
5 GND Ground
6 NC Not connected
7 GND Ground
8 +5V +5 Volts
9 GND Ground
10 +5V +5 Volts