Altera Hybrid Memory Cube Controller - Manual (Page 19)

When you integrate your HMC Controller IP core instance in your design, you must make appropriate
pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level
signals while you are simulating and not ready to map the design to hardware.
When you are ready to map the design to hardware, you must enforce the following constraints:
• Adjacent HMC Controller lanes must map to adjacent Altera device pins. You cannot swap the lane
order by mapping lanes to other Altera device pins. Instead, use the RX mapping and TX mapping
parameters to compensate for board design issues.
• The lanes of an HMC Controller IP core must be configured in no more than three transceiver blocks.
To enforce this constraint, you must configure IP core lanes in transceiver channels with the following
restrictions:
• Lane 0 of a full-width HMC Controller IP core must map to channel 0, 1, or 2 of a transceiver
block.
• If Lane 0 maps to channel 0, then HMC Controller Lane 1 must map to channel 1 of the same
transceiver block (transceiver block N), and Lane 15 maps to channel 3 of the transceiver block
N+2.
• If Lane 0 maps to channel 1, then HMC Controller Lane 1 must map to channel 2 of the same
transceiver block (transceiver block N), and Lane 15 maps to channel 4 of the transceiver block
N+2.
• If Lane 0 maps to channel 2, then HMC Controller Lane 1 must map to channel 3 of the same
transceiver block (transceiver block N), and Lane 15 maps to channel 5 of the transceiver block
N+2.
• Lane 0 of a half-width HMC Controller IP core can map to any channel. If it maps to any of
channels 0, 1, 2, 3, or 4, the IP core lanes are configured in two transceiver blocks.
Required External Blocks
The HMC Controller IP core requires that you define and instantiate the following additional modules:
• One or more external PLL IP cores to configure transceiver TX PLLs for all of the HMC lanes.
Although the hardware these IP cores configure might physically be part of the device transceiver, you
must instantiate them in software separately from the HMC Controller IP core. This requirement
supports the configuration of multiple Altera IP cores using the same transceiver block in the device.
• An external I 2 C master module in your design. Your design must include this module to initialize the
HMC device to which your IP core connects.
2-10 Required External Blocks
UG-01152
2015.05.04
Altera Corporation Getting Started with the HMC Controller IP Core
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