Altera Hybrid Memory Cube Controller - Manual (Page 44)

Signal Name Direction Description
dp_rsp_error Output Indicates that the corresponding request completed with
an error and will not be retried automatically. The HMC
Controller IP core asserts this signal if it received a Read
or Write response packet from the external HMC device
with a non-zero
ERRSTAT
or
DINV
field.
dp_rsp_sop
Output Start of packet. The IP core asserts this signal in the first
cycle of all response transactions.
dp_rsp_eop
Output End of packet. The IP core asserts this signal in the final
cycle of all response transactions.
HMC Controller IP Core Data Path Example
Figure 4-3: Full-Width HMC Controller IP Core Application Interface Example
TAG0 TAG1 TAG2 TAG3
CUBE0 CUBE1 CUBE2 CUBE3
ADDR0 ADDR1 ADDR2 ADDR3
RD16 RD128 WR16 WR128
DATA2 DATA3a DATA3b
TAG0 TAG2 TAG1 TAG3
RD_RS WR_RS RD_RS WR_RS
0x0 0x7
DATA0 DATA1a DATA1b
core_clk
dp_req_valid
dp_req_tag[8:0]
dp_req_cube[2:0]
dp_req_addr[33:0]
dp_req_cmd[5:0]
dp_req_data[511:0]
dp_req_ready
dp_rsp_valid
dp_rsp_tag[8:0]
dp_rsp_cmd[5:0]
dp_rsp_size[2:0]
dp_rsp_data[511:0]
dp_rsp_error
dp_rsp_sop
dp_rsp_eop
dp_req_sop
dp_req_eop
In this example, user logic sends four consecutive request packets and the full-width HMC Controller IP
core sends the corresponding response packets. The first three requests complete without error. The
fourth request completes with an error indication.
UG-01152
2015.05.04
HMC Controller IP Core Data Path Example 4-7
HMC Controller IP Core Signals Altera Corporation
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