Testing features, Testing features -8 – Altera Hybrid Memory Cube Controller User Manual
Page 36
Response Packet Field
Error Indication
INTERRUPT_STATUS Register Bit
SEQ
Unexpected value
SEQ Error
The HMC Controller IP core also checks the
ERRSTAT
field value and treats the response according to the
following rules:
• If
ERRSTAT
has the value of zero, this field indicates no errors or conditions. The IP core processes the
response packet as usual.
• If
ERRSTAT
has a non-zero value in a Read response, Write response, or MODE response packet, the IP
core processes the response as usual, but asserts the
dp_rsp_error
signal on the RX data path interface
when passing the response to the application.
• If
ERRSTAT
has a non-zero value in an Error response packet, the IP core does not forward the Error
response packet to the RX data path interface. Instead, the IP core diverts the packet's
ERRSTAT
and
cube ID values to the internal Error Response FIFO. The first element of the internal Error Response
FIFO is always readable in the
ERROR_RESPONSE
register. You can process these packets in software.
The HMC Controller IP core transmits 32 IRTRY packets in a retry sequence, and expects to receive 20
IRTRY packets from the HMC device.
Related Information
•
Describes the
INTERRUPT_STATUS
interrupt bits
CRC Error
,
SEQ Error
, and
LNG/DLN Error
.
•
Error and Retry Statistics Registers
Describes the
Local Count
field of the
LOCAL_ERROR_COUNT
register.
•
on page 5-5
Describes the
ERROR_RESPONSE
register and the Error Response queue.
Testing Features
The HMC Controller IP core supports multiple testing features.
• You can control the following testing features by writing fields in the HMC Controller IP core
CONTROL
register:
• Force the HMC Controller IP core to detect an error in the input stream and send a StartRetry
request to the HMC device.
• Inject a single-bit error in the CRC of the next request packet.
• Force the Retry State Machine to exit the fatal error state.
• Force the HMC device and the IP core to reset.
• You can use the testing features that the Native PHY IP core provides. You control these features by
writing fields in the hard PCS registers. Write access to these registers is available through the
transceiver reconfiguration interface. If you turn on Enable Altera Debug Master Endpoint (ADME),
write access to these registers is also available through a JTAG master accessible from the Quartus II
System Console.
3-8
Testing Features
UG-01152
2015.05.04
Altera Corporation
Functional Description