Altera Stratix IV GT 100G - Manual (Page 25)

Chapter 6: Board Test System 6–3
Preparing the Board
October 2010 Altera Corporation Stratix IV GT 100G Development Kit User Guide
1 The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
® II Embedded Logic
Analyzer. Because the Quartus II Programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
Preparing the Board
With the power to the board off, perform the following steps:
1. Connect the USB cable to the board.
2. Verify the settings for the board settings DIP switches SW2, SW3, and SW4 match
Figure 4–1 on page 4–2 .
f
For more information about the board’s DIP switch and jumper settings,
refer to the
Stratix IV GT 100G Development Board Reference Manual .
3. Turn the power to the board on.
4. Press PGM_SEL (S10) until the POF 1 LED illuminates, and then press LOAD (S11)
to configure the user hardware portion of flash memory.
c
To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.
Running the Board Test System
To run the application, navigate to the
<install dir>\kits\stratixIVGT_4sgt100g5_100g\examples\board_test_system
directory and run the BoardTestSystem.exe application.
1
On Windows, click Start > All Programs > Altera > Stratix IV GT 100G
Development Kit
<version> > Board Test System to run the application.
A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA. The Stratix IV GT 100G development board’s flash memory ships
preconfigured with the design that corresponds to the test tabs.