Hardware architecture features – Dell 3 User Manual
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PERC 3/DC and PERC 3/DCL Features
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Hardware Architecture Features
Table 5-3 displays the PERC 3/DC and PERC 3/DCL hardware architecture
features.
More than 200 qtags per array
Yes
Hardware clustering support on the board
Yes
User-specified rebuild rate
Yes
Ta b l e 5 - 3 . H a r d w a r e A r c h i t e c t u r e Fe a t u r e s
Specification
Feature
Processor
Intel i960RN 100MHz
SCSI controller(s)
One QLogic
®
12160 Dual SCSI
controller
Size of flash ROM
1 MB
Amount of non-volatile random access
memory (NVRAM)
32 KB
Hardware-exclusive OR (XOR)
assistance
Yes
Direct input/output (I/O)
Yes
SCSI bus termination
Active, single-ended or low voltage
differential (LVD)
Double-sided dual in-line memory
modules (DIMMs)
Yes
Auxiliary TermPWR source
No
Direct I/O bandwidth
533 MB/s (greater than 200 MB/s
sustained)
Ta b l e 5 - 2 . C o n f i g u r a t i o n o n D i s k Fe a t u r e s
(continued)
Specification
Feature