Dell 3 - Manual (Page 81)

PERC 3/QC Features 79
PCI Bridge/CPU
PERC 3/QC uses the Intel i960RN PCI bridge with an embedded i960RN
RISC processor running at 100 MHz. The RN bridge handles data transfers
between the primary (host) PCI bus, the secondary PCI bus, cache memory,
and the SCSI bus. The DMA controller supports chaining and unaligned
data transfers. The embedded i960JN CPU directs all controller functions,
including command processing, SCSI bus transfers, RAID processing, drive
rebuilding, cache management, and error recovery.
Cache Memory
128 MB of PERC 3/QC cache memory resides in a memory bank that uses a
64 MB or 128 MB SDRAM DIMM. PERC 3/QC supports write-through or
write-back caching, selectable for each logical drive. To improve
performance in sequential disk accesses, the PERC 3/QC controller uses
read-ahead caching by default. You can disable read-ahead caching.
Operating voltage 5 V, 3.3 V
SCSI controller Four SCSI controllers for 160M and Wide
support.
SCSI data transfer rate Up to 160 MB/s per channel
SCSI bus LVD or single-ended
SCSI termination Active
Termination disable Automatic through cable and device detection
Devices per SCSI channel Up to 15 wide or seven narrow SCSI devices.
SCSI device types Synchronous or asynchronous.
RAID levels supported 0, 1, 5, 10, and 50
SCSI connectors Two 68-pin internal high-density connectors for
16-bit SCSI devices. Four ultra-high density 68-
pin external connectors for 160M and Wide
SCSI.
Serial port 9-pin RS232C-compatible connector (for
manufacturing use only)
Ta b l e 6 - 7 . P E R C 3 / Q C S p e c i f i c a t i o n s (continued)
Parameter Specification