Avago Technologies LSI53C1020 - Manual (Page 135)

External Memory Timing Diagrams 5-15
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Figure 5.9 NVSRAM Write Cycle
Figure 5.9 NVSRAM Write Cycle (Cont.)
MAD Bus
(Driven by LSI53C1020)
High Order Address
Middle Order
Address
Low Order
Address
FLSHALE1/
(Driven by LSI53C1020)
FLSHALE0/
(Driven by LSI53C1020)
RAMCE/
(Driven by LSI53C1020)
RAMOE/
(Driven by LSI53C1020)
RAMWE0/
(Driven by LSI53C1020)
t
13
t
11
t
12
t
24
t
25
Write
Data
Valid
t
23
t
20
t
27
MAD Bus
(Driven by LSI53C1020)
FLSHALE1/
(Driven by LSI53C1020)
FLSHALE0/
(Driven by LSI53C1020)
RAMCE/
(Driven by LSI53C1020)
RAMOE/
(Driven by LSI53C1020)
RAMWE0/
(Driven by LSI53C1020)
t
24
t
25
t
21
Valid Write Data
t
20
t
23
t
22
t
26
t
27