Avago Technologies LSI53C1020 - Manual (Page 47)

Ultra320 SCSI Functional Description 2-21
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
agreement or a paced transfer agreement before performing packetized
transfers.
The number of bytes in an information unit transfer is always a multiple
of four. If the number of bytes to transfer in the information unit is not a
multiple of four, the LSI53C1020 transmits pad bytes to bring the byte
count to a multiple of four.
2.4.1.5 Quick Arbitration and Selection (QAS)
When using packetized transfers, QAS allows devices to arbitrate for the
bus immediately after the message phase. QAS reduces the bus
overhead and maximizes bus bandwidth by skipping the bus free phase
that normally follows a SCSI connection.
To perform QAS, the target sends a QAS request message to the initiator
during the message phase of the bus. QAS-capable devices snoop the
SCSI bus for the QAS request message. If a QAS request message is
seen, devices can immediately move to the arbitration phase without
going to the bus free phase. The LSI53C1020 employs a fairness
algorithm to ensure that all devices have equal bus access.
2.4.1.6 Skew Compensation
The LSI53C1020 provides a method to account for and control system
skew between the clock and data signals. Skew compensation is only
available when the device operates in the Ultra320 SCSI mode. The
initiator-target pair uses the training sequences in the SPI-4 draft
standard to determine the skew compensation. Depending on the state
of the RTI bit in the PPR negotiation, the LSI53C1020 can either execute
this training pattern during each connection, or can execute the training
pattern, store the adjustment parameters, and recall them on subsequent
connections with the given device. The target determines when to
execute the training pattern.
2.4.1.7 Cyclic Redundancy Check (CRC)
Ultra320 SCSI and Ultra160 SCSI devices employ CRC as an error
detection code during the DT Data phases. These devices transfer four
CRC bytes during the DT Data phases to ensure reliable data transfers.