Avago Technologies LSI53C1020 - Manual (Page 138)

5-18 Specifications
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Table 5.19 and Figure 5.11 provide the timing information for Flash ROM
write accesses.
Table 5.19 Flash ROM Write Cycle
Symbol Parameter Min Max Unit
t
11
Address setup to FLSHALE/ HIGH 25 – ns
t
12
Address hold from FLSHALE/ HIGH 25 – ns
t
13
FLSHALE/ pulse width 25 – ns
t
20
Data setup to RAMWE0/ LOW 40 – ns
t
21
Data hold from RAMWE0/ HIGH 30 – ns
t
22
RAMWE0/ pulse width 20 – ns
t
23
Address setup to RAMWE0/ LOW 75 – ns
t
24
FLSHCE/ LOW to RAMWE0/ HIGH 60 – ns
t
25
FLSHCE/ LOW to RAMWE0/ LOW 25 – ns
t
26
RAMWE0/ HIGH to RAMCE/ HIGH 25 – ns
t
27
FLSHCE/ pulse width 100 – ns