Avago Technologies LSI53C1020 - Manual (Page 136)

5-16 Specifications
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
5.4.2 Flash ROM Timing
Table 5.18 and Figure 5.10 provide the timing information for Flash ROM
read accesses.
Table 5.18 Flash ROM Read Cycle Timing
Symbol Parameter Min Max Unit
t
1
Address setup to FLSHALE/ HIGH 25 – ns
t
2
Address hold from FLSHALE/ HIGH 25 – ns
t
3
FLSHALE/ pulse width 25 – ns
t
4
Address valid to data clocked in 135 – ns
t
5
FLSHCE/ LOW to data clocked in 85 – ns
t
6
RAMOE/ LOW to data clocked in 75 – ns
t
7
Data setup to RAMOE/ HIGH 10 – ns
t
8
Data setup to FLSHCE/ HIGH 10 – ns
t
9
Data hold from FLSHCE/ HIGH 0 – ns