Avago Technologies LSI53C1020 - Manual (Page 26)

1-12 Introduction
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
• Provides 2 kV electrostatic discharge (ESD) protection on SCSI
signals
• Provides latch-up protection greater than 150 mA
• Provides voltage feed-through protection
• Supports the Integrated RAID (IR) solution to provide physical
mirroring or striping of the boot volume
• Has a high proportion of power and ground pins
• Provides power and ground isolation of I/O pads and internal chip
logic
• Supports CRC checking and generation in double transition (DT)
phases
• Provides comprehensive SureLINK Domain Validation technology:
– Basic (Level 1) with inquiry command
– Enhanced (Level 2) with read/write buffer
– Margined (Level 3) with margining of drive strength and slew
rates
• Supports TolerANT technology, which provides:
– Active negation of SCSI Data, Parity, Request, and Acknowledge
signals for improved SCSI transfer rates
– Input signal filtering on SCSI receivers for improved data
integrity, even in noisy cabling environments
1.8.6 Testability
These features enhance the testability of the LSI53C1020:
• Allows all SCSI signals to be accessed through programmed I/O
• Supports JTAG boundary scan
• Provides ARM Multi-ICE
®
test interface for debugging purposes