Avago Technologies LSI53C1020 - Manual (Page 34)

2-8 Functional Description
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
The doorbell mechanism provides both a high-priority communication
path that interrupts the host system device driver and an alternative
communication path to the message queues. Because data transport
through the system doorbell occurs a single dword at a time, use the
LSI53C1020 message queues for normal operation and data transport.
2.3 PCI Functional Description
The host PCI interface complies with the PCI Local Bus Specification,
Revision 2.2 (LSI53C1020 controller), or Revision 2.3 (LSI53C1020A
controller) and with the PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0a. The LSI53C1020 supports up to a 133 MHz,
64-bit PCI-X bus. The LSI53C1020 provides support for 64-bit
addressing with Dual Address Cycle (DAC).
2.3.1 PCI Addressing
The three physical address spaces the PCI specification defines are:
•
PCI Configuration Space
•
PCI I/O Space for operating registers
•
PCI Memory Space for operating registers
The following sections describe the PCI address spaces.
2.3.1.1 PCI Configuration Space
The LSI53C1020 defines the PCI Configuration Space registers for the
PCI function. The configuration space is a contiguous 256 x 8-bit set of
addresses. The system BIOS initializes the configuration registers using
PCI configuration cycles. The LSI53C1020 decodes C_BE[3:0]/ to
determine if a PCI cycle intends to access the configuration register
space. The IDSEL signal behaves as a chip select signal that enables
access to the configuration register space only. The LSI53C1020 ignores
configuration read/write cycles when IDSEL is not asserted.
2.3.1.2 PCI I/O Space
The PCI specification defines I/O Space as a contiguous, 32-bit I/O
address that all system resources share, including the LSI53C1020. The