Document Outline

• Contents
• Preface
  • About this document
    • Intended audience
    • Using this manual
    • Typographical conventions
    • Product revision status
    • Timing diagram conventions
    • Further reading
      • ARM publications
      • Other publications
• 1 Introduction
  • 1.1 About the ARM720T processor
    • 1.1.1 EmbeddedICE-RT logic
      • Changes to the programmer’s model
  • 1.2 Coprocessors
  • 1.3 About the instruction set
    • 1.3.1 Format summary
    • 1.3.2 ARM instruction set
    • 1.3.3 Thumb instruction set
  • 1.4 Silicon revisions
• 2 Programmer’s Model
  • 2.1 Processor operating states
    • 2.1.1 Switching between processor states
      • Entering Thumb state
      • Entering ARM state
  • 2.2 Memory formats
    • 2.2.1 Big-endian format
    • 2.2.2 Little-endian format
  • 2.3 Instruction length
  • 2.4 Data types
  • 2.5 Operating modes
    • 2.5.1 Changing operating modes
  • 2.6 Registers
    • 2.6.1 The ARM state register set
      • Interrupt modes
    • 2.6.2 The Thumb state register set
    • 2.6.3 The relationship between ARM and Thumb state registers
    • 2.6.4 Accessing high registers in Thumb state
  • 2.7 Program status registers
    • 2.7.1 The condition code flags
    • 2.7.2 The control bits
    • 2.7.3 Reserved bits
  • 2.8 Exceptions
    • 2.8.1 Action on entering an exception
    • 2.8.2 Action on leaving an exception
    • 2.8.3 Exception entry and exit summary
    • 2.8.4 Fast interrupt request
    • 2.8.5 Interrupt request
    • 2.8.6 Abort
    • 2.8.7 Software interrupt
    • 2.8.8 Undefined instruction
    • 2.8.9 Exception vectors
    • 2.8.10 Exception priorities
    • 2.8.11 Exception restrictions
  • 2.9 Relocation of low virtual addresses by the FCSE PID
  • 2.10 Reset
  • 2.11 Implementation-defined behavior of instructions
    • 2.11.1 Indexed addressing on a Data Abort
    • 2.11.2 Early termination
• 3 Configuration
  • 3.1 About configuration
    • 3.1.1 Compatibility
    • 3.1.2 Notation
  • 3.2 Internal coprocessor instructions
  • 3.3 Registers
    • 3.3.1 ID Register
    • 3.3.2 Control Register
      • Enabling the MMU
    • 3.3.3 Translation Table Base Register
    • 3.3.4 Domain Access Control Register
    • 3.3.5 Fault Status Register
    • 3.3.6 Fault Address Register
    • 3.3.7 Cache Operations Register
    • 3.3.8 TLB Operations Register
    • 3.3.9 Process Identifier Registers
      • Fast Context Switch Extension Process Identifier Register
      • Changing FCSE PID
      • Trace Process Identifier Register
    • 3.3.10 Register 14, reserved
    • 3.3.11 Test Register
• 4 Instruction and Data Cache
  • 4.1 About the instruction and data cache
    • 4.1.1 IDC operation
    • 4.1.2 Cachable bit
      • Cachable reads (C=1)
      • Uncachable reads (C=0)
    • 4.1.3 Read-lock-write
  • 4.2 IDC validity
    • 4.2.1 Software IDC flush
    • 4.2.2 Doubly-mapped space
  • 4.3 IDC enable, disable, and reset
• 5 Write Buffer
  • 5.1 About the write buffer
    • 5.1.1 Bufferable bit
  • 5.2 Write buffer operation
    • 5.2.1 Bufferable write
    • 5.2.2 Unbufferable write
    • 5.2.3 Read-lock-write
    • 5.2.4 Reading from a noncachable area
    • 5.2.5 Draining the write buffer
    • 5.2.6 Multi-word writes
• 6 The Bus Interface
  • 6.1 About the bus interface
    • 6.1.1 Summary of the AHB transfer mechanism
  • 6.2 Bus interface signals
  • 6.3 Transfer types
  • 6.4 Address and control signals
    • 6.4.1 HADDR[31:0]
    • 6.4.2 HWRITE
    • 6.4.3 HSIZE[2:0]
    • 6.4.4 HBURST[2:0]
    • 6.4.5 HPROT[3:0]
  • 6.5 Slave transfer response signals
    • 6.5.1 HREADY
    • 6.5.2 HRESP[1:0]
  • 6.6 Data buses
    • 6.6.1 HWDATA[31:0]
    • 6.6.2 HRDATA[31:0]
    • 6.6.3 Endianness
  • 6.7 Arbitration
    • 6.7.1 HBUSREQ
    • 6.7.2 HLOCK
    • 6.7.3 HGRANT
  • 6.8 Bus clocking
    • 6.8.1 HCLK
    • 6.8.2 HCLKEN
  • 6.9 Reset
• 7 Memory Management Unit
  • 7.1 About the MMU
    • 7.1.1 Access permissions and domains
    • 7.1.2 Translated entries
  • 7.2 MMU program-accessible registers
  • 7.3 Address translation
    • 7.3.1 Translation Table Base Register
    • 7.3.2 Level one fetch
    • 7.3.3 Level one descriptor
    • 7.3.4 Section descriptor
    • 7.3.5 Coarse page table descriptor
    • 7.3.6 Fine page table descriptor
    • 7.3.7 Translating section references
    • 7.3.8 Level two descriptor
    • 7.3.9 Translating large page references
    • 7.3.10 Translating small page references
    • 7.3.11 Translating tiny page references
    • 7.3.12 Subpages
  • 7.4 MMU faults and CPU aborts
  • 7.5 Fault address and fault status registers
    • 7.5.1 Fault Status
  • 7.6 Domain access control
  • 7.7 Fault checking sequence
    • 7.7.1 Alignment fault
    • 7.7.2 Translation fault
    • 7.7.3 Domain fault
    • 7.7.4 Permission fault
  • 7.8 External aborts
  • 7.9 Interaction of the MMU and cache
    • 7.9.1 Enabling the MMU
    • 7.9.2 Disabling the MMU
• 8 Coprocessor Interface
  • 8.1 About coprocessors
    • 8.1.1 Coprocessor availability
  • 8.2 Coprocessor interface signals
  • 8.3 Pipeline-following signals
  • 8.4 Coprocessor interface handshaking
    • 8.4.1 The coprocessor
    • 8.4.2 The ARM720T core
    • 8.4.3 Coprocessor signaling
    • 8.4.4 Consequences of busywaiting
    • 8.4.5 Coprocessor register transfer instructions
    • 8.4.6 Coprocessor data operations
    • 8.4.7 Coprocessor load and store operations
  • 8.5 Connecting coprocessors
    • 8.5.1 Connecting a single coprocessor
    • 8.5.2 Connecting multiple coprocessors
  • 8.6 Not using an external coprocessor
  • 8.7 STC operations
  • 8.8 Undefined instructions
  • 8.9 Privileged instructions
• 9 Debugging Your System
  • 9.1 About debugging your system
    • 9.1.1 A typical debug system
  • 9.2 Controlling debugging
    • 9.2.1 Debug modes
    • 9.2.2 Examining system state during debugging
  • 9.3 Entry into debug state
    • 9.3.1 Entry into debug state on breakpoint
    • 9.3.2 Entry into debug state on watchpoint
    • 9.3.3 Entry into debug state on debug request
    • 9.3.4 Action of the ARM720T processor in debug state
    • 9.3.5 Clocks
  • 9.4 Debug interface
    • 9.4.1 Debug interface signals
  • 9.5 ARM720T core clock domains
  • 9.6 The EmbeddedICE-RT macrocell
  • 9.7 Disabling EmbeddedICE-RT
  • 9.8 EmbeddedICE-RT register map
  • 9.9 Monitor mode debugging
    • 9.9.1 Enabling monitor mode
    • 9.9.2 Restrictions on monitor-mode debugging
  • 9.10 The debug communications channel
    • 9.10.1 Domain Access Control Register
      • Instructions
    • 9.10.2 Communications through the DCC
      • Sending a message to the debugger
      • Receiving a message from the debugger
  • 9.11 Scan chains and the JTAG interface
    • 9.11.1 Scan chain implementation
      • Scan chain 1
      • Scan chain 2
      • Scan chain 15
    • 9.11.2 Controlling the JTAG interface
  • 9.12 The TAP controller
    • 9.12.1 Resetting the TAP controller
  • 9.13 Public JTAG instructions
    • 9.13.1 SCAN_N (b0010)
    • 9.13.2 INTEST (b1100)
    • 9.13.3 IDCODE (b1110)
    • 9.13.4 BYPASS (b1111)
    • 9.13.5 RESTART (b0100)
  • 9.14 Test data registers
    • 9.14.1 Bypass register
    • 9.14.2 ARM720T processor device identification (ID) code register
    • 9.14.3 Instruction register
    • 9.14.4 Scan path select register
    • 9.14.5 Scan chains 1 and 2
      • Scan chain 1
      • Scan chain 2
  • 9.15 Scan timing
    • 9.15.1 Scan chain 1 cells
  • 9.16 Examining the core and the system in debug state
    • 9.16.1 Determining the core state
    • 9.16.2 Determining system state
  • 9.17 Exit from debug state
  • 9.18 The program counter during debug
    • 9.18.1 Breakpoints
    • 9.18.2 Watchpoints
    • 9.18.3 Watchpoint with another exception
    • 9.18.4 Debug request
    • 9.18.5 System speed access
    • 9.18.6 Summary of return address calculations
  • 9.19 Priorities and exceptions
    • 9.19.1 Breakpoint with Prefetch Abort
    • 9.19.2 Interrupts
    • 9.19.3 Data Aborts
  • 9.20 Watchpoint unit registers
    • 9.20.1 Programming and reading watchpoint registers
    • 9.20.2 Using the data, and address mask registers
    • 9.20.3 The watchpoint unit control registers
  • 9.21 Programming breakpoints
    • 9.21.1 Hardware breakpoints
    • 9.21.2 Software breakpoints
      • Setting the breakpoint
      • Clearing the breakpoint
  • 9.22 Programming watchpoints
  • 9.23 Abort status register
  • 9.24 Debug control register
    • 9.24.1 Disabling interrupts
    • 9.24.2 Forcing DBGRQ
    • 9.24.3 Forcing DBGACK
  • 9.25 Debug status register
  • 9.26 Coupling breakpoints and watchpoints
    • 9.26.1 Breakpoint and watchpoint coupling example
      • CHAINOUT signal
    • 9.26.2 DBGRNG signal
  • 9.27 EmbeddedICE-RT timing
• 10 ETM Interface
  • 10.1 About the ETM interface
  • 10.2 Enabling and disabling the ETM7 interface
  • 10.3 Connections between the ETM7 macrocell and the ARM720T processor
  • 10.4 Clocks and resets
  • 10.5 Debug request wiring
  • 10.6 TAP interface wiring
• 11 Test Support
  • 11.1 About the ARM720T test registers
  • 11.2 Automatic Test Pattern Generation (ATPG)
    • 11.2.1 ARM720T processor INTEST/EXTEST wrapper
      • ATPG
  • 11.3 Test State Register
  • 11.4 Cache test registers and operations
    • 11.4.1 Addressing the CAM and RAM
  • 11.5 MMU test registers and operations
    • 11.5.1 Addressing the CAM, RAM1, and RAM2
  • A.1 AMBA interface signals
  • A.2 Coprocessor interface signals
  • A.3 JTAG and test signals
  • A.4 Debugger signals
  • A.5 Embedded trace macrocell interface signals
  • A.6 ATPG test signals
  • A.7 Miscellaneous signals
• Appendix A Signal Descriptions
• Glossary
• Index