Epson ARM.POWERED ARM720T - Manual (Page 144)

9: Debugging Your System
9-12 EPSON ARM720T CORE CPU MANUAL
9.8 EmbeddedICE-RT register map
The locations of the EmbeddedICE-RT registers are shown in Table 9-1.
9.9 Monitor mode debugging
The ARM720T processor contains logic that enables the debugging of a system without
stopping the core entirely. This means that critical interrupt routines continue to be serviced
while the core is being interrogated by the debugger.
9.9.1 Enabling monitor mode
The debugging mode is controlled by bit 4 of the Debug Control Register (described in Debug
control register on page 9-39). Bit 4 of this register is also known as the monitor mode enable
bit:
Bit 4 set Enables the monitor mode features of the ARM720T processor.
When this bit is set, the EmbeddedICE-RT logic is configured so
that a breakpoint or watchpoint causes the ARM720T core to enter
abort mode, taking the Prefetch or Data Abort vectors respectively.
Bit 4 clear Monitor mode debugging is disabled and the system is placed into
halt mode. In halt mode, the core enters debug state when it
encounters a breakpoint or watchpoint.
Table 9-1 Function and mapping of EmbeddedICE-RT registers
Address Width Function
b00000 6 Debug control
b00001 5 Debug status
b00100 32 Debug Communications Channel (DCC) control register
b00101 32 Debug Communications Channel (DCC) data register
b01000 32 Watchpoint 0 address value
b01001 32 Watchpoint 0 address mask
b01010 32 Watchpoint 0 data value
b01011 32 Watchpoint 0 data mask
b01100 9 Watchpoint 0 control value
b01101 8 Watchpoint 0 control mask
b10000 32 Watchpoint 1address value
b10001 32 Watchpoint 1 address mask
b10010 32 Watchpoint 1 data value
b10011 32 Watchpoint 1 data mask
b10100 9 Watchpoint 1 control value
b10101 8 Watchpoint 1 control mask