Epson ARM.POWERED ARM720T - Manual (Page 32)

1: Introduction
1-12 EPSON ARM720T CORE CPU MANUAL
Addressing mode 4 (store), <a_mode4S>, is shown in Table 1-7.
Addressing mode 5 (coprocessor data transfer), <a_mode5>, is shown in Table 1-8.
Operand 2, <Oprnd2>, is shown in Table 1-9.
Fields, {field}, are shown in Table 1-10.
Table 1-7 Addressing mode 4 (store)
Addressing mode Stack type
IA Increment after EA Empty ascending
IB Increment before FA Full ascending
DA Decrement after ED Empty descending
DB Decrement before FD Full descending
Table 1-8 Addressing mode 5
Operation Assembler
Immediate offset [<Rn>, #+/-<8bit_Offset*4>]
Pre-indexed [<Rn>, #+/-<8bit_Offset*4>]!
Post-indexed [<Rn>], #+/-<8bit_Offset*4>
Table 1-9 Operand 2
Operation Assembler
Immediate value #<32bit_Imm>
Logical shift left <Rm> LSL #<5bit_Imm>
Logical shift right <Rm> LSR #<5bit_Imm>
Arithmetic shift right <Rm> ASR #<5bit_Imm>
Rotate right <Rm> ROR #<5bit_Imm>
Register <Rm>
Logical shift left <Rm> LSL <Rs>
Logical shift right <Rm> LSR <Rs>
Arithmetic shift right <Rm> ASR <Rs>
Rotate right <Rm> ROR <Rs>
Rotate right extended <Rm> RRX
Table 1-10 Fields
Suffix Sets
_c Control field mask bit (bit 3)
_f Flags field mask bit (bit 0)
_s Status field mask bit (bit 1)
_x Extension field mask bit (bit 2)