Epson ARM.POWERED ARM720T - Manual (Page 126)

8: Coprocessor Interface
8-6 EPSON ARM720T CORE CPU MANUAL
8.4.3 Coprocessor signaling
The coprocessor signals as follows:
Coprocessor absent
If a coprocessor cannot accept the instruction currently in Decode
it must leave EXTCPA and EXTCPB both HIGH.
Coprocessor present
If a coprocessor can accept an instruction, and can start that
instruction immediately, it must signal this by driving both
EXTCPA and EXTCPB LOW.
Coprocessor busy (busy-wait)
If a coprocessor can accept an instruction, but is currently unable
to process that request, it can stall the ARM720T core by asserting
busy-wait. This is signaled by driving EXTCPA LOW, but leaving
EXTCPB HIGH. When the coprocessor is ready to start executing
the instruction it signals this by driving EXTCPB LOW. This is
shown in Figure 8-1.
Figure 8-1 Coprocessor busy-wait sequence
8.4.4 Consequences of busy-waiting
A busy-waited coprocessor instruction can be interrupted. If a valid FIQ or IRQ occurs (the
appropriate bit is cleared in the CSPR), the ARM720T processor abandons the coprocessor
instruction, and signals this by taking CPnCPI HIGH. A coprocessor that is capable of
busy-waiting must monitor CPnCPI to detect this condition. When the ARM720T core
abandons a coprocessor instruction, the coprocessor also abandons the instruction and
continues tracking the ARM720T processor pipeline.
Caution:
It is essential that any action taken by the coprocessor while it is busy-waiting is
idempotent. The actions taken by the coprocessor must not corrupt the state of the
coprocessor, and must be repeatable with identical results. The coprocessor can
only change its own state after the instruction has been executed.
ADD SWINE TST CPDO SUB
TST CPDO SUB ADD SWINE
CPDO SUB ADD SWINE TST
I Fetch I Fetch I Fetch I Fetch I Fetch I Fetch I Fetch
(ADD) (SUB) (SWINE) (TST) (CPDO)
coprocessor busy-waiting
HCLK
Fetch stage
Decode stage
Execute stage
CPnCPI (from
core)
EXTCPA (from
coprocessor)
EXTCPB (from
coprocessor)
RDATA[31:0]