Epson ARM.POWERED ARM720T - Manual (Page 36)

1: Introduction
1-16 EPSON ARM720T CORE CPU MANUAL
Shift/Rotate Logical shift left LSL <Rd>, <Rs>, #<5bit_shift_imm> LSL
<Rd>, <Rs>
Logical shift right LSR <Rd>, <Rs>, #<5bit_shift_imm> LSR
<Rd>, <Rs>
Arithmetic shift right ASR <Rd>, <Rs>, #<5bit_shift_imm> ASR
<Rd>, <Rs>
Rotate right ROR <Rd>, <Rs>
Branch Conditional
if Z set BEQ <label>
if Z clear BNE <label>
if C set BCS <label>
if C clear BCC <label>
if N set BMI <label>
if N clear BPL <label>
if V set BVS <label>
if V clear BVC <label>
if C set, and Z clear BHI <label>
if C clear, and Z set BLS <label>
if N set, and V set, or if N
clear, and V clear BGE <label>
if N set, and V clear, or if
N clear, and V set BLT <label>
if Z clear, and N, or V set,
or if Z clear, and N, or V
clear BGT <label>
if Z set, or N set, and V
clear, or N clear, and V
set BLE <label>
Unconditional B <label>
Long branch with link BL <label>
Optional state change
to address held in Lo reg BX <Rs>
to address held in Hi reg BX <Hs>
Load With immediate offset
word LDR <Rd>, [<Rb>, #<7bit_offset>]
halfword LDRH <Rd>, [<Rb>, #<6bit_offset>]
byte LDRB <Rd>, [<Rb>, #<5bit_offset>]
Table 1-12 Thumb instruction summary (continued)
Operation Assembler