Epson ARM.POWERED ARM720T - Manual (Page 214)

Glossary
Glossary-4 EPSON ARM720T CORE CPU MANUAL
Monitor mode
One of two debugging modes. When debugging is performed in monitor
mode, the core does not stop when it encounters a watchpoint or
breakpoint, but enters an abort exception routine. See also Halt mode .
PC
See Program Counter.
Privileged mode
Any processor mode other than User mode. Memory systems typically
check memory accesses from privileged modes against supervisor access
permissions rather than the more restrictive user access permissions. The
use of some instructions is also restricted to privileged modes.
Processor Status Register
See Program Status Register
Program Counter
Register 15, the Program Counter, is used in most instructions as a pointer
to the instruction that is two instructions after the current instruction.
Program Status Register
Contains some information about the current program and some
information about the current processor. Also referred to as Processor
Status Register.
Also referred to as
Current PSR (CPSR), to emphasize the distinction
between it and the Saved PSR (SPSR). The SPSR holds the value the PSR
had when the current function was called, and which will be restored when
control is returned.
PSR
See Program Status Register.
RAZ
Read as zero.
Reduced Instruction Set Computer
A type of microprocessor that recognizes a lower number of instructions in
comparison with a Complex Instruction Set Computer. The advantages of
RISC architectures are:
• they can execute their instructions very fast because the
instructions are so simple
• they require fewer transistors, this makes them cheaper to
produce and more power efficient.
See also Complex Instruction Set Computer.
RISC
See Reduced Instruction Set Computer