Epson ARM.POWERED ARM720T - Manual (Page 91)

6: The Bus Interface
ARM720T CORE CPU MANUAL EPSON 6-11
6.6.2 HRDATA[31:0]
The read data bus is driven by the appropriate slave during read transfers. If the slave extends
the read transfer by holding HREADY LOW, the slave has to provide valid data only at the
end of the final cycle of the transfer, as indicated by HREADY HIGH.
For transfers that are narrower than the width of the bus, the slave only has to provide valid
data on the active byte lanes. The bus master is responsible for selecting the data from the
correct byte lanes. The following tables identify active byte lanes:
• Table 6-6 on page 6-11 shows active byte lanes for little-endian systems
• Table 6-7 on page 6-12 shows active byte lanes for big-endian systems.
A slave has to provide valid data only when a transfer completes with an OKAY response on
HRESP[1:0]. SPLIT, RETRY, and ERROR responses do not require valid read data.
6.6.3 Endianness
It is essential that all modules are of the same endianness and also that any data routing or
bridges are of the same endianness.
Dynamic endianness is not supported, because in most embedded systems, this leads to a
significant silicon overhead that is redundant.
It is recommended that only modules that will be used in a wide variety of applications are
made bi-endian, with either a configuration pin or internal control bit to select the endianness.
For more application-specific blocks, fixing the endianness to either little-endian or big-endian
results in a smaller, lower power, higher performance interface.
Table 6-6 shows active byte lanes for little-endian systems.
Table 6-6 Active byte lanes for a 32-bit little-endian data bus
Transfer size
Address
offset
DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0]
Word 0
Halfword 0 - -
Halfword 2 - -
Byte 0 - - -
Byte 1 - - -
Byte 2 - - -
Byte 3 - - -