Epson ARM.POWERED ARM720T - Manual (Page 102)

7: Memory Management Unit
7-6 EPSON ARM720T CORE CPU MANUAL
7.3.2 Level one fetch
Bits [31:14] of the Translation Table Base Register are concatenated with bits [31:20] of the
MVA to produce a 30-bit address as shown in Figure 7-3.
Figure 7-3 Accessing translation table level one descriptors
This address selects a 4-byte translation table entry. This is a level one descriptor for either a
section or a page table.
7.3.3 Level one descriptor
The level one descriptor returned is either a section descriptor, a coarse page table descriptor,
or a fine page table descriptor, or is invalid. Figure 7-4 shows the format of a level one
descriptor.
Figure 7-4 Level one descriptor
A section descriptor provides the base address of a 1MB block of memory.
The page table descriptors provide the base address of a page table that contains level two
descriptors. There are two sizes of page table:
• coarse page tables have 256 entries, splitting the 1MB that the table describes into
4KB blocks
• fine page tables have 1024 entries, splitting the 1MB that the table describes into
1KB blocks.
31 20 19 0
Table index
31 14 13 0
Translation base
31 14 13 2 1 0
0 0 Table index Translation base
31 0
Level one descriptor
Modified virtual address
Translation table base
31 20 19 12 11 10 9 8 5 4 3 2 1 0
0 0
Coarse page table base address Domain 1 0 1
Section base address AP Domain 1 C B 1 0
Fine page table base address Domain 1 1 1
Fault
Coarse
page table
Section
Fine
page table