Epson ARM.POWERED ARM720T - Manual (Page 37)

1: Introduction
ARM720T CORE CPU MANUAL EPSON 1-17
Note:
All thumb fetches are done as 32-bit bus transactions using the 32-bit thumb
prefetch buffer.
Load With register offset
word LDR <Rd>, [<Rb>, <Ro>]
halfword LDRH <Rd>, [<Rb>, <Ro>]
signed halfword LDRSH <Rd>, [<Rb>, <Ro>]
byte LDRB <Rd>, [<Rb>, <Ro>]
signed byte LDRSB <Rd>, [<Rb>, <Ro>]
PC-relative LDR <Rd>, [PC, #<10bit_offset>]
SP-relative LDR <Rd>, [SP, #<10bit_offset>]
Address
using PC ADD <Rd>, PC, #<10bit_offset>
using SP ADD <Rd>, SP, #<10bit_offset>
Multiple LDMIA Rb!, <reglist>
Store With immediate offset
word STR <Rd>, [<Rb>, #<7bit_offset>]
halfword STRH <Rd>, [<Rb>, #<6bit_offset>]
byte STRB <Rd>, [<Rb>, #<5bit_offset>]
With register offset
word STR <Rd>, [<Rb>, <Ro>]
halfword STRH <Rd>, [<Rb>, <Ro>]
byte STRB <Rd>, [<Rb>, <Ro>]
SP-relative STR <Rd>, [SP, #<10bit_offset>]
Multiple STMIA <Rb>!, <reglist>
Push/Pop Push registers onto stack PUSH <reglist>
Push LR, and registers
onto stack PUSH <reglist, LR>
Pop registers from stack POP <reglist>
Pop registers, and PC
from stack POP <reglist, PC>
Software
Interrupt SWI <8bit_Imm>
Table 1-12 Thumb instruction summary (continued)
Operation Assembler