Epson ARM.POWERED ARM720T - Manual (Page 212)

Glossary
Glossary-2 EPSON ARM720T CORE CPU MANUAL
Complex Instruction Set Computer
A microprocessor that recognizes a large number of instructions.
See also Reduced Instruction Set Computer.
CPSR
See Program Status Register.
Control bits
The bottom eight bits of a program status register. The control bits change
when an exception arises and can be altered by software only when the
processor is in a privileged mode.
Current Program Status Register
See Program Status Register.
DCC
Debug Communications Channel.
Debug state
A condition that allows the monitoring and control of the execution of a
processor. Usually used to find errors in the application program flow. A
processor enters debug state from halt mode and not from monitor mode .
Debugger
A debugging system which includes a program, used to detect, locate, and
correct software faults, together with custom hardware that supports
software debugging.
EmbeddedICE
The EmbeddedICE logic is controlled via the JTAG test access port, using
a protocol converter such as MultiICE: an extra piece of hardware that
allows software tools to debug code running on a target processor.
See also ICE and JTAG.
EmbeddedICE-RT
A version of EmbeddedICE logic that has improved support for real-time
debugging.
Exception modes
Privileged modes that are entered when specific exceptions occur.
Exception
Handles an event. For example, an exception could handle an external
interrupt or an undefined instruction.
External abort
An abort that is generated by the external memory system.
FIQ
Fast interrupt.