Epson ARM.POWERED ARM720T - Manual (Page 24)

1: Introduction
1-4 EPSON ARM720T CORE CPU MANUAL
Changes to the programmer’s model
To provide support for the EmbeddedICE-RT macrocell, the following changes have been made
to the programmer’s model for the ARM720T processor:
Debug Control Register
There are two new bits in the Debug Control Register:
Bit 4
Monitor mode enable. Use this to control how the device reacts on
a breakpoint or watchpoint:
•
When set, the core takes the instruction or data abort
exception.
• When clear, the core enters debug state.
Bit 5 EmbeddedICE-RT disable. Use this when changing watchpoints
and breakpoints:
•
When set, this bit disables breakpoints and watchpoints,
enabling the breakpoint or watchpoint registers to be
programmed with new values.
• When clear, the new breakpoint or watchpoint values become
operational.
For more information, see Debug control register on page 9-39.
Coprocessor register map
A new register, r2, in the coprocessor CP14 register map indicates if the processor
entered the Prefetch or Data Abort exception because of a real abort, or because of a
breakpoint or watchpoint. For more details, see Abort status register on page 9-38.
For more details, see Chapter 9 Debugging Your System .