Epson ARM.POWERED ARM720T - Manual (Page 63)

3: Configuration
ARM720T CORE CPU MANUAL EPSON 3-3
3.3 Registers
The ARM720T processor contains registers that control the cache and MMU operation. You
can access these registers using MCR and MRC instructions to CP15 with the processor in a
privileged mode.
Table 3-1 shows a summary of valid CP15 registers. You must not attempt to read from, or to
write to, an invalid register because it results in Unpredictable behavior.
3.3.1 ID Register
Reading from CP15 Register 0 returns the value:
0x41807204
Note:
The final nibble represents the core revision.
The CRm and opcode_2 fields Should Be Zero when reading CP15 register 0. ID Register read
format is shown in Figure 3-2.
Figure 3-2 ID Register read format
Writing to CP15 register 0 is Unpredictable. ID Register write format is shown in Figure 3-3.
Figure 3-3 ID Register write format
Table 3-1 Cache and MMU Control Register
Register Register reads Register writes
0 ID Register Reserved
1 Control Register Control Register
2 Translation Table Base Register Translation Table Base Register
3 Domain Access Control Register Domain Access Control Register
4 Reserved Reserved
5 Fault Status Register Fault Status Register
6 Fault Address Register Fault Address Register
7 Reserved Cache Operations Register
8 Reserved TLB Operations Register
9 – 12 Reserved Reserved
13 Process Identifier Register Process Identifier Register
14 Reserved Reserved
15 Test Registers Test Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
UNP