Document Outline

• Chapter1 General Description
  • 1.1 TolerANT® Technology
  • 1.2 LSI53C810A Benefits Summary
    • 1.2.1 SCSI Performance
    • 1.2.2 PCI Performance
    • 1.2.3 Integration
    • 1.2.4 Ease of Use
    • 1.2.5 Flexibility
    • 1.2.6 Reliability
    • 1.2.7 Testability
      • Figure1.1 LSI53C810A System Diagram
      • Figure1.2 LSI53C810A Chip Block Diagram
• Chapter2 Functional Description
  • 2.1 SCSI Core
    • 2.1.1 DMA Core
  • 2.2 SCRIPTS Processor
    • 2.2.1 SDMS Software: The Total SCSI Solution
  • 2.3 Prefetching SCRIPTS Instructions
    • 2.3.1 Opcode Fetch Burst Capability
  • 2.4 PCI Cache Mode
    • 2.4.1 Load and Store Instructions
    • 2.4.2 3.3 V/5 V PCI Interface
    • 2.4.3 Loopback Mode
  • 2.5 Parity Options
    • Table 2.1 Bits Used for Parity Control and Observation
    • Table 2.2 SCSI Parity Control
    • Table 2.3 SCSI Parity Errors and Interrupts
    • 2.5.1 DMA FIFO
      • Figure2.1 DMA FIFO Sections
      • 2.5.1.1 Data Paths
        • Figure2.2 LSI53C810A Host Interface Data Paths
  • 2.6 SCSI Bus Interface
    • 2.6.1 Terminator Networks
    • 2.6.2 Select/Reselect During Selection/Reselection
      • Figure2.3 Active or Regulated Termination
    • 2.6.3 Synchronous Operation
      • 2.6.3.1 Determining the Data Transfer Rate
      • 2.6.3.2 SCNTL3 Register, Bits [6:4] (SCF[2:0])
      • 2.6.3.3 SCNTL3 Register, Bits [2:0] (CCF[2:0])
      • 2.6.3.4 SXFER Register, Bits [7:5] (TP[2:0])
      • 2.6.3.5 Achieving Optimal SCSI Send Rates
        • Figure2.4 Determining the Synchronous Transfer Rate
  • 2.7 Interrupt Handling
    • 2.7.1 Polling and Hardware Interrupts
      • 2.7.1.1 Registers
      • 2.7.1.2 Fatal vs. Nonfatal Interrupts
      • 2.7.1.3 Masking
      • 2.7.1.4 Stacked Interrupts
      • 2.7.1.5 Halting in an Orderly Fashion
      • 2.7.1.6 Sample Interrupt Service Routine
• Chapter3 PCI Functional Description
  • 3.1 PCI Addressing
    • 3.1.1 Configuration Space
    • 3.1.2 PCI Bus Commands and Functions Supported
      • 3.1.2.1 I/O Read Command
      • 3.1.2.2 I/O Write Command
      • 3.1.2.3 Memory Read Command
      • 3.1.2.4 Memory Read Multiple Command
      • 3.1.2.5 Memory Read Line Command
      • 3.1.2.6 Memory Write Command
      • 3.1.2.7 Memory Write and Invalidate Command
  • 3.2 PCI Cache Mode
    • 3.2.1 Support for PCI Cache Line Size Register
    • 3.2.2 Selection of Cache Line Size
    • 3.2.3 Alignment
      • 3.2.3.1 MMOV Misalignment
      • 3.2.3.2 Memory Write and Invalidate Command
      • 3.2.3.3 Memory Read Line Command
    • 3.2.4 Memory Read Multiple Command
    • 3.2.5 Unsupported PCI Commands
      • Table 3.1 PCI Bus Commands and Encoding Types
  • 3.3 Configuration Registers
    • Table 3.2 PCI Configuration Register Map
• Chapter4 Signal Descriptions
  • Figure4.1 LSI53C810A Pin Diagram
  • Table 4.1 Power and Ground Signals
  • Figure4.2 Functional Signal Grouping
  • 4.1 PCI Bus Interface Signals
    • 4.1.1 System Signals
      • Table 4.2 System Signals
    • 4.1.2 Address and Data Signals
      • Table 4.3 Address and Data Signals
    • 4.1.3 Interface Control Signals
      • Table 4.4 Interface Control Signals
    • 4.1.4 Arbitration Signals
      • Table 4.5 Arbitration Signals
    • 4.1.5 Error Reporting Signals
      • Table 4.6 Error Reporting Signals
  • 4.2 SCSI Bus Interface Signals
    • 4.2.1 SCSI Bus Interface Signals
      • Table 4.7 SCSI Bus Interface Signals
    • 4.2.2 Additional Interface Signals
      • Table 4.8 Additional Interface Signals
• Chapter5 Operating Registers
  • Figure5.1 Register Address Map
  • Table 5.1 Synchronous Clock Conversion Factor
  • Table 5.2 Asynchronous Clock Conversion Factor
  • Table 5.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1
  • Table 5.4 Examples of Synchronous Transfer Periods and Rates for Fast SCSI
  • Table 5.5 SCSI Synchronous Offset Values
• Chapter6 Instruction Set of the I/O Processor
  • 6.1 Low Level Register Interface Mode
  • 6.2 SCSI SCRIPTS
    • Table 6.1 SCRIPTS Instructions
    • 6.2.1 Sample Operation
      • Figure6.1 SCRIPTS Overview
  • 6.3 Block Move Instructions
    • 6.3.1 First Dword
      • Figure6.2 Block Move Instruction Register
    • 6.3.2 Second Dword
  • 6.4 I/O Instruction
    • 6.4.1 First Dword
      • Figure6.3 I/O Instruction Register
    • 6.4.2 Second Dword
  • 6.5 Read/Write Instructions
    • 6.5.1 First Dword
    • 6.5.2 Second Dword
    • 6.5.3 Read-Modify-Write Cycles
    • 6.5.4 Move To/From SFBR Cycles
      • Figure6.4 Read/Write Register Instruction
      • Table 6.2 Read/Write Instructions
  • 6.6 Transfer Control Instructions
    • 6.6.1 First Dword
      • Figure6.5 Transfer Control Instruction
    • 6.6.2 Second Dword
  • 6.7 Memory Move Instructions
    • Figure6.6 Memory to Memory Move Instruction
    • 6.7.1 First Dword
    • 6.7.2 Second Dword
    • 6.7.3 Third Dword
    • 6.7.4 Read/Write System Memory from a SCRIPTS Instruction
  • 6.8 Load and Store Instructions
    • 6.8.1 First Dword
    • 6.8.2 Second Dword
      • Figure6.7 Load and Store Instruction Format
• Chapter7 Electrical Characteristics
  • 7.1 DC Characteristics
    • Table 7.1 Absolute Maximum Stress Ratings
    • Table 7.2 Operating Conditions
    • Table 7.3 SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/
    • Table 7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
    • Table 7.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN
    • Table 7.6 Capacitance
    • Table 7.7 Output Signals—MAC/_TESTOUT, REQ/
    • Table 7.8 Output Signal—IRQ/
    • Table 7.9 Output Signal—SERR/
    • Table 7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR...
    • Table 7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/
  • 7.2 TolerANT Technology
    • Table 7.12 TolerANT Technology Electrical Characteristics
    • Figure7.1 Rise and Fall Time Test Conditions
    • Figure7.2 SCSI Input Filtering
    • Figure7.3 Hysteresis of SCSI Receiver
    • Figure7.4 Input Current as a Function of Input Voltage
    • Figure7.5 Output Current as a Function of Output Voltage
  • 7.3 AC Characteristics
    • Table 7.13 Clock Timing
    • Figure7.6 Clock Timing
    • Table 7.14 Reset Input Timing
    • Figure7.7 Reset Input
    • Table 7.15 Interrupt Output
    • Figure7.8 Interrupt Output Waveforms
  • 7.4 PCI Interface Timing Diagrams
    • 7.4.1 Target Timing
      • Figure7.9 PCI Configuration Register Read
      • Figure7.10 PCI Configuration Register Write
      • Figure7.11 Target Read
      • Figure7.12 Target Write
    • 7.4.2 Initiator Timing
      • Figure7.13 OpCode Fetch, Nonburst
      • Figure7.14 Burst Opcode Fetch
      • Figure7.15 Back-to-Back Read
      • Figure7.16 Back-to-Back Write
      • Figure7.17 Burst Read
      • Figure7.18 Burst Write
  • 7.5 PCI Interface Timing
    • Table 7.16 PCI Timing
  • 7.6 SCSI Timings
    • Table 7.17 Initiator Asynchronous Send (5 Mbytes/s)
    • Figure7.19 Initiator Asynchronous Send
    • Table 7.18 Initiator Asynchronous Receive (5 Mbytes/s)
    • Figure7.20 Initiator Asynchronous Receive
    • Table 7.19 Target Asynchronous Send (5 Mbytes/s)
    • Figure7.21 Target Asynchronous Send
    • Table 7.20 Target Asynchronous Receive (5 Mbytes/s)
    • Figure7.22 Target Asynchronous Receive
    • Figure7.23 Initiator and Target Synchronous Transfers
    • Table 7.21 SCSI-1 Transfers (SE, 5.0 Mbytes/s)
    • Table 7.22 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 40 MHz Clock)
    • Table 7.23 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 50 MHz Clock)
  • 7.7 Package Drawings
    • Figure7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2)
• AppendixA Register Summary
  • TableA.1 Configuration Registers
  • TableA.2 SCSI Registers
• Index
• Customer Feedback