LSI 53C810A - Manual (Page 152)

6-12 Instruction Set of the I/O Processor
TC[23:0] Transfer Counter [23:0]
This 24-bit field specifies the number of data bytes to be
moved between the LSI53C810A and system memory.
The field is stored in the
DMA Byte Counter (DBC)
register. When the LSI53C810A transfers data to/from
memory, the
DMA Byte Counter (DBC) register is
decremented by the number of bytes transferred. In
addition, the
DMA Next Address (DNAD) register is
incremented by the number of bytes transferred. This
process is repeated until the
DMA Byte Counter (DBC)
register has been decremented to zero. At that time, the
LSI53C810A fetches the next instruction.
If bit 28 is set, indicating table indirect addressing, this
field is not used. The byte count is instead fetched from
a table pointed to by the
Data Structure Address (DSA)
register.
6.3.2 Second Dword
Start Address [31:0]
This 32-bit field specifies the starting address of the data
to be moved to/from memory. This field is copied to the
DMA Next Address (DNAD) register. When the
LSI53C810A transfers data to or from memory, the DMA
Next Address (DNAD) register is incremented by the
number of bytes transferred.
When bit 29 is set, indicating indirect addressing, this
address is a pointer to an address in memory that points
to the data location. When bit 28 is set, indicating table
MSG C_D I_O SCSI Phase
0 0 0 Data-Out
0 0 1 Data-In
0 1 0 Command
0 1 1 Status
1 0 0 Reserved-Out
1 0 1 Reserved-In
1 1 0 Message-Out
1 1 1 Message-In