LSI 53C810A - Manual (Page 55)

Configuration Registers 3-13
EIS Enable I/O Space 0
This bit controls the LSI53C810A’s response to I/O space
accesses. A value of zero disables the response. A value
of one allows the LSI53C810A to respond to I/O space
accesses at the address specified in
Base Address Zero
(I/O) .
Register: 0x06
Status
Read/Write
The Status register is used to record status information for PCI
bus-related events.
In the LSI53C810A, bits 0 through 4 are reserved and bits 5, 6, 7, and
11 are not implemented.
Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is cleared whenever the register is
written, and the data in the corresponding bit location is a one. For
instance, to clear bit 15 and not affect any other bits, write the value
0x8000 to the register.
DPE Detected Parity Error (from Slave) 15
This bit is set by the LSI53C810A whenever it detects a
data parity error, even if parity error handling is disabled.
SSE Signaled System Error 14
This bit is set whenever a device asserts the SERR/
signal.
RMA Master Abort (from Master) 13
A master device should set this bit whenever its
transaction (except for Special Cycle) is terminated with
master-abort. All master devices should implement this
bit.
15 14 13 12 11 10 9 8 7 0
DPE SSE RMA RTA R DT[1:0] DPR R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0