4 stacked interrupts – LSI 53C810A User Manual
Page 39
Interrupt Handling
2-19
whether polling or hardware interrupts are being used; whether the
interrupt is fatal or nonfatal; and whether the chip is operating in the
Initiator or Target mode.
If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the
SCSI Interrupt Status Zero (SIST0)
or
SCSI Interrupt Status One (SIST1)
is still set, the SIP bit in the
is not set, and the IRQ/ pin is not asserted. See
Section 2.7.1.2, “Fatal vs. Nonfatal Interrupts,”
for a list of the nonfatal
interrupts.
If a fatal interrupt is masked and that condition occurs, then the SCRIPTS
still stop, the appropriate bit in the
,
, or
SCSI Interrupt Status One (SIST1)
register is
set, and the SIP or DIP bits in the
is set, but the
IRQ/ pin is not asserted.
When the chip is initialized, enable all fatal interrupts if you are using
hardware interrupts. If a fatal interrupt is disabled and that interrupt
condition occurs, the SCRIPTS halt and the system never knows it
unless it times out and checks the ISTAT after a certain period of
inactivity.
If you are polling the ISTAT instead of using hardware interrupts, then
masking a fatal interrupt makes no difference since the SIP and DIP bits
in the
inform the system of interrupts, not the
IRQ/ pin.
Masking an interrupt after IRQ/ is asserted does not cause deassertion
of IRQ/.
2.7.1.4 Stacked Interrupts
The LSI53C810A will stack interrupts if they occur one after the other. If
the SIP or DIP bits in the ISTAT register are set (first level), then there is
already at least one pending interrupt, and any future interrupts are
stacked in extra registers behind the
SCSI Interrupt Status Zero (SIST0)
,
SCSI Interrupt Status One (SIST1)
, and
registers
(second level). When two interrupts have occurred and the two levels of
the stack are full, any further interrupts set additional bits in the extra
registers behind
SCSI Interrupt Status Zero (SIST0)
,
, and
. When the first level of