LSI 53C810A - Manual (Page 18)

1-6 General Description
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Controlled bus assertion times (reduces RFI, improves reliability, and
eases FCC certification)
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Latch-up protection greater than 150 mA
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Voltage feed-through protection (minimum leakage current through
SCSI pads)
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High proportion (> 25%) of pins power and ground
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Power and ground isolation of I/O pads and internal chip logic
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TolerANT technology, which provides:
– Active negation of SCSI Data, Parity, Request, and Acknowledge
signals for improved fast SCSI transfer rates.
– Input signal filtering on SCSI receivers improves data integrity,
even in noisy cabling environments.
1.2.7 Testability
The LSI53C810A provides improved testability through:
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Access to all SCSI signals through programmed I/O
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SCSI loopback diagnostics
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SCSI bus signal continuity checking
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Support for single step mode operation
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Test mode (AND tree) to check pin continuity to the board
A system diagram showing the connections of the LSI53C810A in a PCI
system is pictured in
Figure 1.1 . A block diagram of the LSI53C810A is
pictured in Figure 1.2 .