LSI 53C810A - Manual (Page 224)

IX-2 Index
clock address incrementor bit 5-36
clock byte counter bit 5-36
clock conversion factor bits 5-10
CLSE bit 5-45
CM bit 5-31
CMP bit 5-48
,
5-51
COM bit 5-47
CON bit 5-7
,
5-28
configured as I/O bit 5-31
configured as memory bit 5-31
connected bit 5-7
,
5-28
CSF bit 5-64
CTEST0 register 5-29
CTEST1 register 5-30
CTEST2 register 5-30
CTEST4 register 5-34
CTEST5 register 5-36
CTEST6 register 5-37
cycle frame 4-7
D
DACK bit 5-31
data acknowledge status bit 5-31
data path 2-8
data request status bit 5-31
data structure address register 5-26
data transfer direction bit 5-30
dataRD bit 5-56
dataWR bit
DWR bit 5-56
DBC register 5-38
DC characteristics 7-1
DCMD register 5-39
DCNTL register 5-45
DDIR bit 5-30
,
5-37
destination I/O-memory enable bit 5-42
determining the data transfer rate 2-13
device select 4-7
DEVSEL/ 4-7
DF[7:0] bits 5-37
DFE bit 5-21
DFIFO register 5-33
DHP bit 5-6
DIEN register 5-44
DIFFSENS SCSI signal 7-3
DIOM bit 5-42
DIP bit 5-29
disable halt on parity error or ATN bit 5-6
disable single initiator response bit 5-64
DMA byte counter register 5-38
DMA command register 5-39
DMA control register 5-45
DMA core 2-2
DMA direction bit 5-37
DMA FIFO 2-8
DMA FIFO bits 5-37
DMA FIFO empty bit 5-21
DMA FIFO register 5-33
DMA interrupt enable register 5-44
DMA interrupt pending bit 5-29
DMA mode register 5-41
DMA next address register 5-39
DMA SCRIPTS pointer register 5-39
DMA SCRIPTS pointer save register 5-40
DMA status register 5-20
DMODE register 5-41
DNAD register 5-39
DRD bit 5-56
DREQ bit 5-31
DSA register 5-26
DSI bit 5-64
DSP register 5-39
DSPS register 5-40
DSTAT register 5-20
E
ease of use 1-4
enable parity checking bit 5-5
enable read line bit 5-42
enable read multiple bit 5-43
enable response to reselection bit 5-11
enable response to selection bit 5-11
encoded destination SCSI ID bits 5-15
,
5-19
EPC bit 5-5
ERL bit 5-42
EXC bit 5-6
EXT bit 5-63
extend SREQ/SACK filtering bit 5-63
extra clock cycle of data setup bit 5-6
F
FBL[2:0] bits 5-36
fetch enable bit 5-57
fetch opcode bursting 2-4
FF[3:0] bits 5-24
FFL[3:0] bits 5-30
FIFO byte control bits 5-36
FIFO flags bits 5-24
FMT[3:0] bits 5-30
FRAME/ 4-7
function complete bit 5-48
,
5-51
G
GEN bit 5-50
,
5-54
GEN[3:0] bits 5-58
general purpose bits 5-16
general purpose pin control register 5-56
general purpose register 5-16
general purpose timer expired bit 5-50
,
5-54
general purpose timer period bits 5-58
GNT/ 4-8
GPCNTL register 5-56
GPIO enable bits 5-57
GPIO[1:0] bits 5-16
GPIO_EN[1:0] bits 5-57
GPREG register 5-16
grant 4-8
H
halt SCSI clock bit
HSC bit 5-64
handshake-to-handshake timer expired bit 5-50
,
5-54
handshake-to-handshake timer period bits 5-57
header type (HT[7:0]) 3-17
high impedance mode bit 5-35
HTH bit 5-50
,
5-54