LSI 53C810A - Manual (Page 155)

I/O Instruction 6-15
Wait Select Instruction
1. If the LSI53C810A is selected, it fetches the next
instruction from the address pointed to by the DMA
SCRIPTS Pointer (DSP) register.
2. If reselected, the LSI53C810A fetches the next
instruction from the address pointed to by the 32-bit
jump address field stored in the
DMA Next Address
(DNAD) register. Manually set the LSI53C810A to
Initiator mode when it is reselected.
3. If the CPU sets the SIGP bit in the SCSI Status Zero
(SSTAT0) register, the LSI53C810A aborts the Wait
Select instruction and fetches the next instruction from
the address pointed to by the 32-bit jump address
field stored in the
DMA Next Address (DNAD) register.
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the
SCSI Output Control Latch
(SOCL) register are set. Do not set SACK/ or SATN/
except for testing purposes. When the target bit is set,
the corresponding bit in the
SCSI Control Zero (SCNTL0)
register is also set. When the carry bit is set, the
corresponding bit in the Arithmetic Logic Unit (ALU) is
set.
Note: None of the signals are set on the SCSI bus in Target
mode.