LSI 53C810A - Manual (Page 16)

1-4 General Description
1.2.2 PCI Performance
To improve PCI performance, the LSI53C810A:
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Bursts 2, 4, 8, or 16 Dwords across PCI bus with 80-byte DMA FIFO
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Prefetches up to 8 Dwords of SCRIPTS instructions
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Supports 32-bit word data bursts with variable burst lengths.
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Bursts SCRIPTS opcode fetches across the PCI bus
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Performs zero wait-state bus master data bursts faster than
110 Mbytes/s (@ 33 MHz)
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Supports PCI Cache Line Size register
1.2.3 Integration
Features of the LSI53C810A which ease integration include:
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3.3 V/5 V PCI interface
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Full 32-bit PCI DMA bus master
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DMA controller using Memory-to-Memory Move instructions
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High-performance SCSI core
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Integrated SCRIPTS processor
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Compact 100-pin PQFP packaging
1.2.4 Ease of Use
The LSI53C810A provides:
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Direct PCI-to-SCSI connection
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Reduced SCSI development effort
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Support for the ASPI software standard using SDMS software
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Compatibility with existing LSI53C7XX and LSI53C8XX family
SCRIPTS
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Direct connection to PCI and SCSI SE bus
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Development tools and sample SCSI SCRIPTS
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Maskable and pollable interrupts