Index ix-5 – LSI 53C810A User Manual

Page 227

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Index

IX-5

0x41

5-50

0x42

5-51

0x43

5-53

0x44

5-54

0x46

5-55

0x47

5-56

0x48

5-57

0x49

5-58

0x4A

5-59

0x4C

5-60

0x4D

5-61

0x4E

5-62

0x4F

5-63

0x50

5-65

0x54

5-66

0x58

5-66

PCI configuration registers

0x00

3-11

0x02

3-11

0x04

3-11

0x06

3-13

0x08

3-15

0x09

3-15

0x0C

3-16

0x0D

3-16

0x0E

3-17

0x10

3-17

0x14

3-17

0x3C

3-18

0x3D

3-18

0x3E

3-19

0x3F

3-19

encoded chip SCSI ID, bits

5-12

register bits

abort operation

5-26

aborted

5-21

,

5-44

arbitration in progress

5-23

arbitration mode

5-3

arbitration priority encoder test

5-60

assert even SCSI parity

5-7

assert SATN/ on parity error

5-5

assert SCSI ACK

5-18

assert SCSI ATN/

5-18

assert SCSI BSY/

5-18

assert SCSI C_D/

5-18

assert SCSI data bus

5-6

assert SCSI I_O/

5-18

assert SCSI MSG/

5-18

assert SCSI REQ/ signal

5-18

assert SCSI RST/ signal

5-7

assert SCSI SEL/

5-18

burst disable

5-34

burst length

5-41

burst mode fetch enable

5-43

bus fault

5-44

byte empty in DMA FIFO

5-30

byte full in DMA FIFO

5-30

byte offset counter

5-33

cache line size enable

5-45

chip revision level

5-32

chip type

5-55

clear DMA FIFO

5-32

clear SCSI FIFO

5-64

clock address incrementor

5-36

clock byte counter

5-36

clock conversion factor

5-10

configured as I/O

5-31

configured as memory

5-31

connected

5-7

,

5-28

DACK

5-31

data transfer direction

5-30

dataRD

5-56

dataWR

5-56

destination I/O-memory enable

5-42

disable halt on parity error

5-6

disable single initiator response

5-64

DMA direction

5-37

DMA FIFO

5-37

DMA FIFO empty bit

5-21

DMA interrupt pending

5-29

DREQ

5-31

enable parity checking

5-5

enable read line

5-42

enable read multiple

5-43

enable response to reselection

5-11

enable response to selection

5-11

encoded destination ID

5-15

encoded destination SCSI ID

5-19

extend SREQ/SACK filtering

5-63

extra clock cycle of data setup

5-6

fetch enable

5-57

fetch pin mode

5-32

FIFO byte control

5-36

FIFO flags

5-24

flush DMA FIFO

5-32

function complete

5-48

,

5-51

general purpose timer expired

5-50

,

5-54

general purpose timer period

5-58

GPIO enable

5-57

GPIO[1:0]

5-16

halt SCSI clock

5-64

handshake-to-handshake timer expired

5-50

,

5-54

handshake-to-handshake timer period

5-57

high impedance mode

5-35

illegal instruction detected

5-22

,

5-44

immediate arbitration

5-7

interrupt-on-the-fly

5-28

IRQ disable

5-46

IRQ mode

5-46

last disconnect

5-25

latched SCSI parity

5-24

lost arbitration

5-23

LSI53C700 family compatibility

5-47

manual start mode

5-43

master control for set or reset pulses

5-37

master data parity error

5-21

,

5-44

master enable

5-56

master parity error enable

5-35

max SCSI synchronous offset

5-14

parity error

5-53

phase mismatch or SATN/ active

5-51

pointer SCRIPTS

5-56

prefetch enable

5-45

prefetch flush

5-45

reselected

5-48

,

5-52

reset SCSI offset

5-62

SACK/ status

5-20

SATN/ status

5-20

SBSY/ status

5-20

SC_D/ status

5-20

SCLK

5-61

SCRIPTS

5-56

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